MPEG video bitstream decoder system and method

ABSTRACT

A method and apparatus is provided for generating various binary addresses for use in decoding MPEG video data. One or more n-bit counters and mutiplexers are used to generate such binary addresses. Different binary addresses can be generated by the same n-bit counter by swapping the bits of the n-bit counter. The number of different binary addresses that an n-bit counter can generate is n factorial.

FIELD OF THE INVENTION

[0001] This invention relates to MPEG video technology and, morespecifically, to decoding Motion Picture Experts Group (MPEG) videobitstream.

BACKGROUND OF THE INVENTION

[0002] In MPEG technology, the compressed digital system signal, orbitstream, which includes a video portion, an audio portion, and otherinformational portions, is transmitted to a receiver. Transmission maybe over existing television channels, cable television channels,satellite communication channels, and the like.

[0003] A decoder is provided at the receiver to de-multiplex, decompressand decode the received system signal in accordance with a givencompression algorithm. The decoded video and audio information is thenoutput to a display device such as a television monitor for presentationto the user.

[0004] Video and audio compression and encoding is performed by suitableencoders which implement a selected data compression algorithm thatconforms to a recognized standard or specification agreed to among thesenders and receivers of digital video signals. Highly efficientcompression standards have been developed by the Moving Pictures ExpertsGroup (MPEG), including MPEG-1 and MPEG-2. The MPEG standards enableseveral VCR-like viewing options such as Normal Forward, Play, SlowForward, Fast Forward, Fast Reverse, and Freeze.

[0005] The MPEG specification defines a hierarchical data structure inthe video portion of the bitstream. A video sequence includes a sequenceheader, one or more groups of pictures, and an end-of-sequence code. Agroup of pictures is a series of one or more pictures intended to allowrandom access into the sequence.

[0006] A picture is the primary coding unit of a video sequence. Apicture consists of three rectangular matrices representing luminance(Y) and two chrominance (Cb, Cr) values. The Y matrix has an even numberof rows and columns. The Cb and Cr matrices are one-half the size of theY matrix in each direction (horizontal and vertical). Thus, for everyfour luminance values, there are two associated chrominance values (oneCb value and one Cr value).

[0007] A slice is one or more contiguous macroblocks. Slices areimportant in the handling of errors. If the bitstream contains an error,the decoder can skip to the start of the next slice.

[0008] A macroblock is a 16×16 line section of luminance components andthe corresponding chrominance components. A block is an 8×8 set ofvalues of a luminance or chrominance component.

[0009] The MPEG standard defines three main types of video pictures:

[0010] 1. Intracoded pictures (I-pictures) which are coded withoutreference to any other pictures.

[0011] 2. Predictive-coded pictures (P-pictures) which are coded usingmotion-compensated forward prediction from a previous I or P referencepicture.

[0012] 3. Bidirectional predictive-coded pictures (B-pictures) which arecoded using interpolated motion compensation from a previous and afuture I or P picture.

[0013] I pictures are coded using only the Discrete Cosine Transform(DCT) which converts time and space domain into frequency and amplitudedomain for the purpose of achieving data compression.

[0014] The macroblock is the basic motion compensation unit for P and Bpictures. Each macroblock is coded by computing a motion compensationvector which defines the displacement between the macroblock, and thecorresponding macroblock in the reference I or P picture(s) from whichit is being predicted. If there is little or no motion, the motioncompensation vector will not be transmitted.

[0015] A comparison macroblock is then generated by displacing thereference macroblock by the amount indicated by the motion compensationvector, which is then subtracted from the macroblock of the P or Bpicture that is being coded to produce an error signal which correspondsto the difference therebetween. The error signal is then coded using DCT(similar to an intracoded picture) and transmitted with the motionvector. If, however, the error signal is small or zero, no errorcomponent is transmitted.

[0016] Thus, a predictive coded macroblock (P or B) can consist of onlya motion compensation component, only a transform (DCT) coded component,or both.

[0017] After motion compensation and DCT coding are performed, themacroblock is quantized, and Variable Length Coded (VLC) to furthercompress the data bitstream. The macroblocks are then assembled intoslices, pictures, groups of pictures and video sequences, multiplexedwith associated audio data, and transmitted to a user for decoding andpresentation.

[0018] The basic idea behind MPEG video compression is to remove spatialredundancy within a video frame and temporal redundancy between videoframes. As in JPEG, the standard for still image compression, DCT-based(Discrete Cosine Transform) compression is used to reduce spatialredundancy. Motion- compensation is used to exploit temporal redundancy.The images in a video stream usually do not change much within smalltime intervals. The idea of motion-compensation is to encode a videoframe based on other video frames temporally close to it.

[0019] A video stream is a sequence of video frames. Each frame is astill image. A video player displays one frame after another, usually ata rate close to 30 frames per second (23.976, 24, 25, 29.97, 30).

[0020] Frames are digitized in a standard RGB format, 24 bits per pixel(8 bits each for Red, Green, and Blue). MPEG-1 is designed to producebit rates of 1.5 Mb/s or less, and is intended to be used with images ofsize 352×288 at 24-30 frames per second. This results in data rates of55.7-69.6 Mb/s.

[0021] Frames are divided into 16×16 pixel macroblocks. Each macroblockconsists of four 8×8 luminance blocks and two 8×8 chrominance blocks(1 Uand 1 V). Macroblocks are the units for motion-compensated compression.Blocks are used for DCT compression. Frames can be encoded in threetypes: intra-frames (I-frames), forward predicted frames (P-frames), andbi-directional predicted frames (B-frames).

[0022] An MPEG-1 video sequence is an ordered stream of bits, with aspecial bit pattern sequences marking the beginning and ending of alogical section.

[0023] Typically, in real-time MPEG video decoders, which are used intoday's set-top boxes or DVD players, a decoding algorithm inapplication-specific integrated circuits (ASIC's) is implemented. Insuch cases, key functional operations such as Variable Length Decoding(VLD), Inverse Zig-Zag Scan (IZZ), Inverse Quantization (IQ), InverseDiscrete Cosine Transform (IDCT), Motion Compensation (MC) and Merge andStore (MS) are mapped to dedicated hardware, herein referred to asapplication specific integrated circuits (ASICs) In one approach, theMPEG bitstream that is to be decoded is stored in a DRAM buffer in adecoder system. The MPEG bitstream that is to be decoded is hereinreferred to as “bitstream”.

[0024]FIG. 1 is a simplified block diagram that illustrates somecomponents of a typical MPEG-2 video bitstream decoder core. In FIG. 1,reconstructed data 102 is the bitstream that is to be decoded and isshown as an input into the dynamic random access memory (DRAM) interface104. DRAM interface 104 is communicatively coupled to DRAM buffer 106,MC module 108, VLD/IZZ/Q module 114 and MS module 112. In addition, MCmodule 108 is communicatively coupled to MC buffer 110, which in turn iscommunicatively coupled to MS module 112. VLD/IZZ/IQ module 114 iscommunicatively coupled to IDCT module 116, which in turn iscommunicatively coupled to IDCT buffer 118.

[0025] The data and data paths referred to herein are associated withreconstructed data 102. There are two main data paths for decodingreconstructed data 102: 1) one data path is for spatial datareconstruction, and 2) one data path is for temporal datareconstruction. The spatial data path goes through the VLD/IZZ/IQ module114 and IDCT module 116, and the resulting data is written into IDCTbuffer 118. The temporal data path, which comprises MC module 108, getsreference data from previously reconstructed data stored in memory. Theresulting data coming out of MC module 108 is written to MC buffer 110.

[0026] In the final steps of data reconstruction, MS module 112 performsthe following: 1) reads in spatial data from the IDCT buffer and readsin temporal data from the MC buffer, 2) adds the data that is read fromthe MC buffer to the data that is read from the IDCT buffer to produce acombined data set of reconstructed data, and 3) writes the combined dataset to DRAM buffer 106 where the reconstructed data is stored

[0027] All the above operations involve data fetch and store indifferent addressing schemes. The spatial data path is block based or8×8 based, while the temporal data path is macroblock based or 16×16based or 16×8 based. Thus, the MS module handles both block based andmacroblock based addressing schemes when adding spatial and temporaldata together. In addition, there are many flags in the bitstream whichmake the IDCT/MC buffer accessing mechanism quite complicated.

[0028] In one approach, the ASIC implementation of MPEG video decoding,such as the decoding performed by VLD/IZZ/IQ, IDCT, MC and MS modules,is designed using a pipeline architecture. In a pipeline architecture,the IDCT buffer and the MC buffer require different read/write addresspattern sequences. Traditionally, each buffer has its own associatedaddress generator in order to simultaneously facilitate data access. Thedrawback of pipeline architecture is more hardware consumption, which inturn consumes more power.

[0029] Therefore, in past approaches, decoders require a large amount ofhardware in terms of gate count and power consumption. Because of thehigher level of logic complexity, the effort required to test and debuga decoder is also large. Also, the different addressing schemes of eachdata path in the decoding process require different types addressgenerators.

[0030] Based on the foregoing, there is a need for a method or mechanismfor unifying addressing schemes used in MPEG decoding.

SUMMARY OF THE INVENTION

[0031] A mechanism is provided for decoding video signals. According toone aspect of the invention, an n-bit counter is used to generate up ton factorial (n!) number of distinct bit pattern sequences. One or moreof the distinct n! number of bit sequences are selected to createcorresponding one or more addressing schemes. The data that isassociated with the video signals are fetched and stored using the oneor more addressing schemes. The one or more addressing schemes are basedon corresponding one or more flags and condition that are associatedwith data.

[0032] According to one feature of the invention, the n-bit counter isused to produced a first sequence of 2^(n) sequential numbers, whereineach of the 2^(n) sequential numbers is associated with a distinctbinary value comprising n bits. An mth pair of bits in each binary valueis swapped to produce a (m+1)th sequence of 2^(n) number ofnon-sequential numbers, wherein m equals (n!−1). According to anotherfeature, one or more multiplexers are used to select the one or more n!number of distinct bit pattern sequences.

[0033] According to another feature of the invention, when the mth pairof bits in each binary value is swapped, a pre-determined combinationallogic is applied to the swapped bits.

[0034] According to one feature of the invention, the logic of anaddress generator is simplified by using an n-bit counter, which is thesimplest sequence generator, and by swapping bits. Thus, hardware costis reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The present invention is illustrated by way of example, and notby way of limitation, in the figures of the accompanying drawings and inwhich like reference numerals refer to similar elements and in which:

[0036]FIG. 1 is a simplified block diagram that illustrates somecomponents of a typical MPEG-2 video bitstream decoder core;

[0037]FIG. 2 is a simplified block diagram that illustrates some keycomponents that replace the IDCT module and IDCT buffer of FIG. 1;

[0038]FIG. 3 is a simplified block diagram that illustrates some keycomponents that replace the MC module and MC buffer of FIG. 1;

[0039]FIG. 4 is a simplified block diagram that illustrates some keycomponents that replace the MS module of FIG. 1;

[0040]FIG. 5 is a block diagram of an address generator used in certainembodiments of the invention;

[0041]FIG. 6 is a block diagram of another variation of an addressgenerator according to certain embodiments of the invention;

[0042]FIG. 7 is a block diagram that illustrates the data format inmemory;

[0043]FIG. 8 is a block diagram that illustrates three differentchrominance formats for a macroblock;

[0044]FIG. 9 is a block diagram that illustrates one address patternsequence that can be used for a 4:2:0 chrominance format;

[0045]FIG. 10 is a block diagram that illustrates one address patternsequence that can be used for a 4:2:2 chrominance format;

[0046]FIG. 11 is a block diagram that illustrates one address patternsequence that can be used for a 4:4:4 chrominance format;

[0047]FIG. 12 is a block diagram that illustrates one address patternsequence that can be used for a 4:2:0 chrominance format;

[0048]FIG. 13 is a block diagram that illustrates one address patternsequence that can be used for a 4:2:2 chrominance format;

[0049]FIG. 14 is a block diagram that illustrates one address patternsequence that can be used for a 4:4:4 chrominance format;

[0050]FIG. 15 is a block diagram that illustrates one address patternsequence that can be used for a 4:2:0 chrominance format;

[0051]FIG. 16 is a block diagram that illustrates one address patternsequence that can be used for a 4:2:2 chrominance format;

[0052]FIG. 17 is a block diagram that illustrates one address patternsequence that can be used for a 4:4:4 chrominance format;

[0053]FIG. 18 is a block diagram that illustrates one address patternsequence that can be used for a 4:2.0 chrominance format;

[0054]FIG. 19 is a block diagram that illustrates one address patternsequence that can be used for a 4:2:2 chrominance format; and

[0055]FIG. 20 is a block diagram that illustrates one address patternsequence that can be used for a 4:4:4 chrominance format.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0056] A method and system are described for decoding MPEG videobitstream. In the following description, for the purposes ofexplanation, numerous specific details are set forth in order to providea thorough understanding of the present invention. It will be apparent,however, to one skilled in the art that the present invention may bepracticed without these specific details In other instances, well-knownstructures and devices are shown in block diagram form in order to avoidunnecessarily obscuring the present invention.

OPERATIONAL AND FUNCTIONAL OVERVIEW

[0057] The decoding process as performed by the IDCT module 116, IDCTbuffer 118, MC module 108, MC buffer 110 and MS module 112 are describedherein with reference to FIG. 1, FIG. 2, FIG. 3 and FIG. 4. Referring toFIG. 1, DRAM buffer is partitioned for constructed (bitstream) data andreconstructed (decoded data) data Constructed data 102 is stored in theDRAM buffer 106 through DRAM interface 104 and is fed to VLD/IZZ/IQmodule 114 and IDCT 116 through DRAM interface 104 for decoding. TheIDCT 116 processes macroblock data that is associated with constructeddata 102. After processing, IDCT 116 writes the macroblock data to IDCTbuffer 118 based on coded block pattern. Any current non-coded block inthe IDCT buffer will maintain the value of the previous coded blockvalue. Reconstructed data from DRAM buffer 106 are also fed to MC module108. If motion compensation exists in the macroblock data that isassociated with constructed data 102, then MC module 108 retrievesreference data, which is previously reconstructed data that is stored inDRAM buffer 106. MC module 108 processes the macroblock data and writesthe macroblock data to MC buffer 110.

[0058] MS module 112 reads the macroblock data from IDCT buffer 118 andfrom MC buffer 110 and adds the macroblock data together before sendingthe resulting macroblock data back to DRAM buffer 106.

[0059] The decoding process performed by IDCT buffer 118, MC buffer 110and MS module 112 involve multiple read/write events. Each read/writeevent is associated with a distinct bit pattern sequence based on thedifferent motion compensation modes and residue modes present in theconstructed data. In addition, the read/write events are also based onthe conditions and/or flags that are associated with the constructeddata that is to be decoded. Such conditions and flags are decoded beforereconstructing each macroblock of data. Examples of typical motioncompensation modes are: 1) frame, 2) field, 3) 8×16, and 4) dual prime.Typical residue modes are: 1) frame, and 2) field. Different read/writeaddress pattern sequences are associated with each mode.

[0060] According to certain embodiments of the invention, rather thanusing several mechanisms to perform the different read/write addresspattern sequences associated with each mode, a single unified mechanismis provided to perform the different read/write sequences as performedby IDCT buffer 118, MC buffer 1110 and MS module 112.

[0061] Some of the important details of the unified mechanism forperforming the different read/write sequences, according to certainembodiments of the invention, are described herein with reference toFIG. 2, FIG. 3 and FIG. 4. According to certain embodiments, the unifiedmechanism for performing the different read/write address patternsequences is based on using the same type of address generator in theIDCT, MC and MS modules. The address generators use a bit swappingtechnique for generating the different read/write address patternsequences and are further described in greater detail herein.

[0062]FIG. 2 is a simplified block diagram that illustrates some keycomponents that replace IDCT module 116 and IDCT buffer 118 of FIG. 1.In FIG. 2, data 202 from VLD/IZZ/IQ module feeds into IDCT controller204. IDCT controller 204 is a controller that is associated with theIDCT address generator 206 and is thus communicatively coupled with IDCTaddress generator 206. IDCT address generator 206 is communicativelycoupled to the IDCT buffer 208. The IDCT buffer receives a bit patternsequence 212 from an MS module (not shown in FIG. 2) and sends data 210to the MS module. The function of IDCT address generator 206 is furtherdescribed in greater detail herein under the section ADDRESS GENERATORS.

[0063]FIG. 3 is a simplified block diagram that illustrates some keycomponents that replace MC module 108 and MC buffer 110 of FIG. 1. InFIG. 3, reconstructed data 102 from DRAM buffer feeds into MC controller302. MC controller 302 is a controller that is associated with the MCaddress generator 304 and is thus communicatively coupled with MCaddress generator 304. MC address generator 304 is communicativelycoupled to the MC buffer 306. MC buffer 306 receives a bit patternsequence 310 from the MS module (not shown in FIG. 2) and sends data 308to the MS module. The function of MC address generator 304 is furtherdescribed in greater detail herein under the section ADDRESS GENERATOR.

[0064]FIG. 4 is a simplified block diagram that illustrates some keycomponents that replace MS module 112 of FIG. 1. In FIG. 4, MS module402 comprises MS controller 404 that is communicatively coupled to MSaddress generator 406. MS controller 404 controls MS address generator406 The MS address generator 406 sends a bit pattern sequence 410 to theMC buffer (not shown in FIG. 4). Also, MS address generator 406 sendsbit pattern sequence 412 to the IDCT buffer (not shown in FIG. 4). Thefunction of MS address generator 406 is further described in greaterdetail herein under the section ADDRESS GENERATOR.

[0065] Further, MS module 402 receives data 408 from the MC buffer basedon the MS bit pattern sequence 410 and data 416 from the IDCT bufferbased on the MS bit pattern sequence 412. Because the MC buffer and theIDCT buffer send data that has bit pattern sequences that are generatedby MS address generators that has the same timing, albeit different bitpatterns, the MS module only needs one counter to handle data from eachbuffer. Based on the counter and the conditions (e.g. different modes)and flags decoded from the bitstream, the MS address generator swaps thebits to generate different patterns for both the IDCT buffer and the MCbuffer. Thus, MS module 402 needs only one MS address generator tohandle data from both the MC buffer and the IDCT buffer.

[0066] As shown in FIG. 4, MS module 402 adds data 408 and 416 togetherto produce data 414, which is sent to the DRAM buffer for storage (DRAMbuffer is not shown in FIG. 4).

[0067] Address Generator

[0068]FIG. 5 is a block diagram of an address generator used in certainembodiments of the invention. The address generator as shown in FIG. 5comprises an n-bit counter 502, and a multiplexer 504. The n-bit counter502 can generate up to 2^(n) numbers that are sequential, for examplefrom 0 to 2^(n)−1 with an increment of 1. The 2^(n) numbers can berepresented as binary values comprising bits. Each bit has a value ofeither zero or one. Bits can be swapped to produce up to n! number ofbit pattern sequences. Different bit pattern sequences can be used asaddress pattern sequences that are needed for either IDCT buffer or MCbuffer.

[0069] In FIG. 5, 2^(n) number of bit pattern sequences are indicated bypattern_(—)1 508, pattern_(—)2 510, up to pattern_(—)2^(n) 512 as shownin FIG. 5. Through multiplexer 504, which is controlled by an associatedcontroller (not shown in FIG. 5), one of the 2^(n) number of patternsequences in FIG. 5 is selected as output 506. Such a selection is basedupon the conditions and/or flag information that are carried in thereconstructed data, and which are associated with the video signals. Insuch a case, output 506 is the one of the bit pattern sequences frompattern_(—)1 508 to pattern_(—)2^(n) 512. Further, the counter's valuecontrols the multiplexer 504 for selecting one of the bit patternsequences from pattern_(—)1 508 to pattern_(—)2^(n) 512 as output 506.In such case, the output is composed of different ranges of two or morebit pattern sequences from pattern_(—)1 508 to pattern_(—)2^(n) 512.

[0070] When bits are swapped, the resulting output will no longer remainsequential. Each time the bits are swapped, a new bit pattern sequenceis generated. Since n-bit counter 502 has n bits and each bit can be inany position, the total number of possible bit pattern sequences is n!bit pattern sequences. Thus, bit swapping obviates the need for separatededicated hardware for producing different bit pattern sequences thatcan be used in addressing schemes needed for either IDCT buffer or MCbuffer.

[0071] To illustrate, for a 4:2:0 chrominance mode, there are 48 words(6 blocks×8 words=48, each word=8 pixels) in one macroblock. A 6-bitcounter is needed to generate 48 bits with sequential values from 0 to47. The different bit pattern sequences can be generated through themultiplexer by swapping the bits.

[0072]FIG. 6 is a block diagram of another variation of an addressgenerator according to certain embodiments. The address generator asshown in FIG. 6 comprises an n-bit counter 602, and two multiplexers604, and 606. The n-bit counter 602 can generate up to 2^(n) numbersthat are sequential, for example from 0 to 2^(n)−1 with an incrementof 1. Bits can be swapped to produce up to n! number of bit patternsequences. Six bit pattern sequences are shown in FIG. 6 and areindicated by pattern1 612, pattern2 614, pattern3 616, pattern1′618,pattern2′ 620, and pattern3′ 622. Through multiplexer 604, which iscontrolled by an associated controller (not shown in FIG. 6), onepattern sequence is selected as output 608 from among pattern1 612,pattern2 614, pattern3 616. Similarly, through multiplexer 606, one bitpattern sequence is selected as output 610 from among pattern1′ 618,pattern2′ 620, and pattern3′ 622. Such a selection is based upon theconditions and/or flag information carried in the reconstructed data.

[0073] Thus, because the address generator of FIG. 6 can produce, usingone counter, two output bit pattern sequences simultaneously for use indifferent addressing schemes for decoding video signals, the addressgenerator in FIG. 6 is an example of an MS address generator. In FIG. 6,output 608 is a bit pattern sequence associated with the IDCT addressingscheme and output 610 is a bit pattern sequence that is associated withthe MC addressing scheme.

Mathematical Model

[0074] The use of an n-bit counter to produce up to n! pattern sequencesis based on the mathematical model as described herein. An n-bit countercan generate a sequence of sequential numbers that are expressed asn-bit binary values. The n-bit counter can generate up to 2^(n) memoryaddresses

[0075] If mth sequential number produced by the counter may be expressedby the following equation,

m=b(m, n−1)·2^(n−1) +b(m, n−2)·2^(n−2) + . . . +b(m, 1)·2¹ +b(m,0)·2⁰  EQ-1

[0076] where,

[0077] n is the number of bits in the counter

[0078] N=2^(n) is the number memory addresses that the counter cangenerate

[0079] k is the bit position index in the counter {0, 1, 2, . . . n−1}

[0080] i is memory word index {0, 1, 2, N−1}

[0081] b(i, k), where k={0, 1, 2, . . . n−1}, i={0, 1, 2, . . . N−1},represents the set of coefficients in an equation (similar to EQ-1) thatrepresents the ith sequential number produced by the counter

[0082] The mth sequential number produced by the counter may also beexpressed as vector as follows, $\begin{matrix}{m = {\lbrack {{b( {m,{n - 1}} )}\quad {b( {m,{n - 2}} )}\quad \ldots \quad {b( {m,1} )}\quad {b( {m,0} )}} \rbrack_{1 \times n} \cdot \begin{bmatrix}2^{n - 1} \\2^{n - 2} \\\ldots \\2^{1} \\2^{0}\end{bmatrix}_{n \times 1}}} & \text{EQ-2}\end{matrix}$

[0083] Thus, the set of sequential numbers that can be generated by an-bit counter may be expressed as the vector, {right arrow over (C)}, asfollows: $\begin{matrix}{\overset{harpoonup}{C} = {\begin{bmatrix}{b( {0,{n - 1}} )} & {b( {0,{n - 2}} )} & \ldots & {b( {0,1} )} & {b( {0,0} )} \\{b( {1,{n - 1}} )} & {b( {1,{n - 2}} )} & \ldots & {b( {1,1} )} & {b( {1,0} )} \\\ldots & \ldots & \ldots & \ldots & \ldots \\{b( {{N - 2},{n - 1}} )} & {b( {{N - 2},{n - 2}} )} & \ldots & {b( {{N - 2},1} )} & {b( {{N - 2},0} )} \\{b( {{N - 1},{n - 1}} )} & {b( {{N - 1},{n - 2}} )} & \ldots & {b( {{N - 1},1} )} & {b( {{N - 1},0} )}\end{bmatrix}_{N \times n} \cdot \begin{bmatrix}2^{n - 1} \\2^{n - 2} \\\ldots \\2^{1} \\2^{0}\end{bmatrix}_{n \times 1}}} & \text{EQ-3} \\{= {\overset{harpoonup}{B} \cdot \overset{harpoonup}{E}}} & \text{EQ-4}\end{matrix}$

[0084] In EQ-4, {right arrow over (B)} is a matrix of the bit valuesthat correspond to the n sequential numbers. Thus, {right arrow over(B)} is an N×n matrix. The bit values are binary and therefore compriseeither zeros or ones. Each column of the {right arrow over (B)} matrixcontains N/2 zeroes and N/2 ones. Thus, by swapping of one column withanother within the {right arrow over (B)} matrix will produce anon-repeating sequence of numbers when {right arrow over (B)}·{rightarrow over (E)}. The swapping of columns in the {right arrow over (B)}matrix is equivalent to swapping bits in the n-bit counter.

[0085] The mathematical expression that is associated with bit swappingis further detailed by the following equations: $\begin{matrix}{C = {\overset{harpoonup}{B} \cdot \overset{harpoonup}{E}}} & \text{EQ-5} \\{= {\begin{bmatrix}{b( {0,{n - 1}} )} & {b( {0,{n - 2}} )} & \ldots & {b( {0,s} )} & \ldots & {b( {0,t} )} & \ldots & {b( {0,1} )} & {b( {0,0} )} \\{b( {1,{n - 1}} )} & {b( {1,{n - 2}} )} & \ldots & {b( {1,s} )} & \ldots & {b( {1,t} )} & \ldots & {b( {1,1} )} & {b( {1,0} )} \\\ldots & \ldots & \ldots & \ldots & \ldots & \ldots & \ldots & \ldots & \ldots \\{b( {{N - 2},{n - 1}} )} & {b( {{N - 2},{n - 2}} )} & \ldots & {b( {{N - 2},s} )} & \ldots & {b( {{N - 2},t} )} & \ldots & {b( {{N - 2},1} )} & {b( {{N - 2},0} )} \\{b( {{N - 1},{n - 1}} )} & {b( {{N - 1},{n - 2}} )} & \ldots & {b( {{N - 1},s} )} & \ldots & {b( {{N - 1},t} )} & \ldots & {b( {{N - 1},1} )} & {b( {{N - 1},0} )}\end{bmatrix}_{N \times n} \cdot \begin{bmatrix}2^{n - 1} \\2^{n - 2} \\\ldots \\2^{s} \\\ldots \\2^{t} \\\ldots \\2^{1} \\2^{0}\end{bmatrix}_{n \times 1}}} & \text{EQ-6} \\{= {{\begin{bmatrix}{b( {0,{n - 1}} )} & {b( {0,{n - 2}} )} & \ldots & {b( {0,{s + 1}} )} \\{b( {1,{n - 1}} )} & {b( {1,{n - 2}} )} & \ldots & {b( {1,{s + 1}} )} \\\ldots & \ldots & \ldots & \ldots \\{b( {{N - 2},{n - 1}} )} & {b( {{N - 2},{n - 2}} )} & \ldots & {b( {{N - 2},{s + 1}} )} \\{b( {{N - 1},{n - 1}} )} & {b( {{N - 1},{n - 2}} )} & \ldots & {b( {{N - 1},{s + 1}} )}\end{bmatrix}_{N \times {({n - s - 1})}}\begin{bmatrix}2^{n - 1} \\2^{n - 2} \\\quad \\2^{s + 1}\end{bmatrix}}_{{({n - s - 1})} \times 1} + {\begin{bmatrix}{b( {0,s} )} \\{b( {1,s} )} \\\ldots \\{b( {{N - 2},s} )} \\{b( {{N - 1},s} )}\end{bmatrix}_{N \times 1} \cdot \lbrack 2^{s} \rbrack_{1 \times 1}} + {\begin{bmatrix}{b( {0,{s - 1}} )} & {b( {0,{s - 2}} )} & \quad & {b( {0,{t + 1}} )} \\{b( {1,{s - 1}} )} & {b( {1,{s - 2}} )} & \ldots & {b( {1,{t + 1}} )} \\\ldots & \ldots & \ldots & \ldots \\{b( {{N - 2},{s - 1}} )} & {b( {{N - 2},{s - 2}} )} & \ldots & {b( {{N - 2},{t + 1}} )} \\{b( {{N - 1},{s - 1}} )} & {b( {{N - 1},{s - 2}} )} & \ldots & {b( {{N - 1},{t + 1}} )}\end{bmatrix}_{N \times {({s - t - 1})}}\begin{bmatrix}2^{s - 1} \\2^{s - 2} \\\ldots \\2^{t + 1}\end{bmatrix}}_{{({n - s - 1})} \times 1} + {\begin{bmatrix}{b( {0,t} )} \\{b( {1,t} )} \\\ldots \\{b( {{N - 2},t} )} \\{b( {{N - 1},t} )}\end{bmatrix}_{N \times 1} \cdot \lbrack 2^{t} \rbrack_{1 \times 1}} + {\begin{bmatrix}{b( {0,{t - 1}} )} & {b( {0,{t - 2}} )} & \ldots & {b( {0,0} )} \\{b( {1,{t - 1}} )} & {b( {1,{t - 2}} )} & \ldots & {b( {0,1} )} \\\ldots & \ldots & \ldots & \ldots \\{b( {{N - 2},{t - 1}} )} & {b( {{N - 2},{t - 2}} )} & \ldots & {b( {{N - 2},0} )} \\{b( {{N - 1},{t - 1}} )} & {b( {{N - 1},{t - 2}} )} & \ldots & {b( {{N - 1},0} )}\end{bmatrix}_{N \times n} \cdot \begin{bmatrix}2^{t - 1} \\2^{t - 2} \\\ldots \\2^{0}\end{bmatrix}_{n \times 1}}}} & \text{EQ-7} \\{= {{\overset{harpoonup}{C}}_{1} + {2^{s}\begin{bmatrix}{b( {0,s} )} \\{b( {1,s} )} \\\ldots \\{b( {{N - 2},s} )} \\{b( {{N - 1},s} )}\end{bmatrix}}_{N \times 1} + C_{3} + {2^{t}\begin{bmatrix}{b( {0,t} )} \\{b( {1,t} )} \\\ldots \\{b( {{N - 2},t} )} \\{b( {{N - 1},t} )}\end{bmatrix}}_{N \times 1} + C_{5}}} & \text{EQ-8}\end{matrix}$

[0086] Similar with vector {right arrow over (C)}, here is theexpression of vector {right arrow over (C)}, $\begin{matrix}{\overset{harpoonup}{C} = {\overset{harpoonup}{B} \cdot \overset{harpoonup}{E}}} & \text{EQ-9} \\{= {{\overset{harpoonup}{C}}_{1} + {2^{s}\begin{bmatrix}{b( {0,t} )} \\{b( {1,t} )} \\\ldots \\{b( {{N - 2},t} )} \\{b( {{N - 1},t} )}\end{bmatrix}}_{N \times 1} + {\overset{harpoonup}{C}}_{3} + {2^{t}\begin{bmatrix}{b( {0,s} )} \\{b( {1,s} )} \\\ldots \\{b( {{N - 2},s} )} \\{b( {{N - 1},s} )}\end{bmatrix}}_{N \times 1} + {\overset{harpoonup}{C}}_{5}}} & \text{EQ-10}\end{matrix}$

[0087] The relationship between the original sequence of sequentialnumbers generated by the n-bit counter and the subsequent sequence ofnumbers that is generated by swapping bits is as follows.

[0088] From EQ-8 and EQ-10, there are three vectors {right arrow over(C)}₁, {right arrow over (C)}₃, {right arrow over (C)}₅ in both {rightarrow over (C)} and {right arrow over (C)}. To compare the difference ofthese two vectors, we do the followings, $\begin{matrix}{{\overset{harpoonup}{C} - \overset{harpoonup}{C}} = {{2^{s}\begin{bmatrix}{b( {0,s} )} \\{b( {1,s} )} \\\ldots \\{b( {{N - 2},s} )} \\{b( {{N - 1},s} )}\end{bmatrix}}_{N \times 1} + {2^{t}\begin{bmatrix}{b( {0,t} )} \\{b( {1,t} )} \\\ldots \\{b( {{N - 2},t} )} \\{b( {{N - 1},t} )}\end{bmatrix}}_{N \times 1} - ( {{2^{s}\begin{bmatrix}{b( {0,t} )} \\{b( {1,t} )} \\\ldots \\{b( {{N - 2},t} )} \\{b( {{N - 1},t} )}\end{bmatrix}}_{N \times 1} + {2^{t}\begin{bmatrix}{b( {0,s} )} \\{b( {1,s} )} \\\ldots \\{b( {{N - 2},s} )} \\{b( {{N - 1},s} )}\end{bmatrix}}_{N \times 1}} )}} & \text{EQ-11} \\{= {( {2^{s} - 2^{t}} )\begin{bmatrix}{{b( {0,s} )} - {b( {0,t} )}} \\{{b( {1,s} )} - {b( {1,t} )}} \\\ldots \\{{b( {{N - 2},s} )} - {b( {{N - 2},t} )}} \\{{b( {{N - 1},s} )} - {b( {{N - 1},t} )}}\end{bmatrix}}_{N \times 1}} & \text{EQ-12}\end{matrix}$

[0089] Let's stop here and have a more close look at each column of{right arrow over (B)}. For the column k (k is the column index), valuetransition(0−1−0) is every each 2^(k) rows. It is known the total rowsare 2^(n). If the consecutive 0's or 1's are called group, then thenumber of groups G in one column has the following equations,

G·2^(k)=2^(n)  EQ-13

G=2^(n−k)  EQ-14

[0090] The smaller column index, the more groups in one column.

[0091] For the column s and column t(s>t), their total rows are equal,so the group ratio can be get from following equations, $\begin{matrix}{{G_{s} \cdot 2^{s}} = {G_{t} \cdot 2^{t}}} & \text{EQ-15} \\{\frac{G_{t}}{G_{s}} = 2^{s - t}} & \text{EQ-16}\end{matrix}$

[0092] In other words, in each zero group or one group of column s,there are 2^(s−1) zero group and one group in column t, the number ofzero group, and the number of one group are same, each is 2^(s−t−1).From EQ-12, inside the matrix is that column t is subtracted from columns The results are either 0, −1 or 1. So each rows of {right arrow over(C)}−{right arrow over (C)}={0, (2^(s)−2¹), −(2^(s−)−2¹)}. The rowshaving 0's means that after swapping column s and column t, the rowsmaintain same values; the rows having (2^(s)−2¹) means that afterswapping columns, the rows' values added with (2^(s)−2¹); the rowshaving −(2^(s)−2¹) means that after swapping columns, the rowssubtracted with −(2^(s)−2¹).

[0093] Let's take a more close look at column s and column t.

[0094] Based above analysis of column s and column t, continuouslyderive equation EQ12 as following in EQ17, $\begin{matrix}{{\overset{harpoonup}{C} - \overset{harpoonup}{C}} = {{( {2^{s} - 2^{t}} )\begin{bmatrix}{0 - 0} \\\ldots \\{0 - 0} \\{0 - 1} \\\ldots \\{0 - 1} \\\ldots \\{0 - 0} \\\ldots \\{0 - 0} \\{0 - 1} \\\ldots \\{0 - 1} \\{1 - 0} \\\ldots \\{1 - 0} \\{1 - 1} \\\ldots \\{1 - 1} \\\ldots \\{1 - 0} \\\ldots \\{1 - 0} \\{1 - 1} \\\ldots \\{1 - 1} \\{0 - 0} \\\ldots \\\ldots \\{1 - 1}\end{bmatrix}}_{N \times 1} = {{( {2^{s} - 2^{t}} )\begin{bmatrix}0 \\\ldots \\0 \\{- 1} \\\ldots \\{- 1} \\\ldots \\0 \\\ldots \\0 \\{- 1} \\\ldots \\{- 1} \\1 \\\ldots \\1 \\0 \\\ldots \\0 \\\ldots \\1 \\\ldots \\1 \\0 \\\ldots \\0 \\0 \\\ldots \\\ldots \\0\end{bmatrix}}\begin{matrix}{2^{t}\quad {{of}\quad}^{''}0^{''}} & \quad & \quad \\\quad & \quad & \quad \\\quad & \quad & \quad \\{{2^{t}\quad {{of}\quad}^{''}} - 1^{''}} & \quad & \quad \\\quad & {2^{s - t}{groups}} & \quad \\\quad & {{0{s:{2^{s - t - 1} \cdot 2^{t}}}} = 2^{s - 1}} & \quad \\\quad & {{{- 1}{s:{2^{s - t - 1} \cdot 2^{t}}}} = 2^{s - 1}} & \quad \\{2^{t}\quad {{of}\quad}^{''}0^{''}} & \quad & \quad \\\quad & \quad & \quad \\{{2^{t}\quad {{of}\quad}^{''}} - 1^{''}} & \quad & \quad \\\quad & \quad & {{{total}\quad 1{s:{\frac{2^{n - t - 1}}{4} \cdot 2^{t}}}} = 2^{n - 3}} \\{2^{t}\quad {{of}\quad}^{''}1^{''}} & \quad & {{{total}\quad - {1{s:{\frac{2^{n - t - 1}}{4} \cdot 2^{t}}}}} = 2^{n - 3}} \\\quad & \quad & {{{total}{\quad \quad}0{s:{\frac{2^{n - t - 1}}{2} \cdot 2^{t}}}} = 2^{n - 2}} \\\quad & \quad & \quad \\{2^{t}\quad {{of}\quad}^{''}0^{''}} & \quad & \quad \\\quad & \quad & \quad \\\quad & \quad & \quad \\\quad & \quad & \quad \\{2^{t}\quad {{of}\quad}^{''}1^{''}} & \quad & \quad \\\quad & \begin{matrix}{2^{s - t}{groups}} \\{{0{s:{2^{s - t - 1} \cdot 2^{t}}}} = 2^{s - 1}} \\{{{- 1}{s:{2^{s - t - 1} \cdot 2^{t}}}} = 2^{s - 1}}\end{matrix} & \quad \\\quad & \quad & \quad \\\quad & \quad & \quad \\\quad & \quad & \quad \\{2^{t}\quad {{of}\quad}^{''}1^{''}} & \quad & \quad \\\quad & \quad & \quad \\\quad & \quad & \quad \\{2^{t}\quad {{of}\quad}^{''}0^{''}} & \quad & \quad \\\quad & \quad & \quad \\\quad & \quad & \quad\end{matrix}}}} & \text{EQ-17}\end{matrix}$

[0095] From BQ-17, the number of −1's and 1's are same, equal${2^{n - 3} = \frac{N}{4}};$

[0096] the number of 0's are ${2^{n - 2} = \frac{N}{2}};$

[0097] −1's , 1's add together to make N. Corresponding to those rows of0's , the rows maintain same after swapping columns s and t;corresponding to those rows of −1's , offset (2^(s)−2¹) will be takenand compensated to those rows of 1's . Overall are balanced. All thevalue of rows still in the range from 0 to N−1.

[0098] Based on above proof of this mathematical model, the conclusioncan be made: for the matrix

{right arrow over (C)}={right arrow over (B)}·{right arrow over (E)}

[0099] swapping any two columns s and t of matrix {right arrow over(B)}, the result of matrix {right arrow over (C)} have this character:N/2 of its columns remain same, N/4 of its columns offset −(2^(s)−2¹),and (2^(s)−2¹) compensate to the another N/4 rows. The pattern of rowsbeing changed is: in the first 2^(s) rows, skip first 2¹ rows, everyother 2¹ rows have negative offset (2^(s)−2¹); this pattern mirrors tothe second 2^(s), but the rows had negative offset now have positiveoffset; this pattern mirrors to the third 2^(s) rows, in other words,the third 2^(s) rows are same to the first 2^(s) rows. It continuesuntil to the last rows. Here

[0100] {right arrow over (C)}: 1×N vector $\begin{matrix}{\overset{harpoonup}{B} = \begin{bmatrix}0 & 0 & \ldots & 0 & 0 \\0 & 0 & \ldots & 0 & 1 \\0 & 0 & \ldots & 1 & 0 \\0 & 0 & \ldots & 1 & 1 \\\ldots & \ldots & \ldots & \ldots & \ldots \\1 & 1 & 1 & 1 & 0 \\1 & 1 & 1 & 1 & 1\end{bmatrix}_{N \times n}} \\{\overset{harpoonup}{E} = \begin{bmatrix}2^{0} \\2^{1} \\\ldots \\2^{n - 2} \\2^{n - 1}\end{bmatrix}_{n \times 1}} \\{N = 2^{- 2}}\end{matrix}$

[0101] s, t: column index, s>t; 0<s−t≦n−1

[0102] It can be seen from above, if swap any columns of {right arrowover (B)}, another new vector of {right arrow over (C)} can be generatedwith above mentioned characters. So to generate a new vector {rightarrow over (C)} the maximum patterns are n!, since there are n! ways ofpositioning each columns of {right arrow over (B)}.

[0103] Bit Swappping

[0104] For the purpose of explanation, assume a 4-bit counter. The{right arrow over (B)} matrix for a 4-bit counter is of size 16×4 andappears as follows.

[0105] If {right arrow over (C)} represents the sequential numbers thatcan be produced by the 4-bit counter, then {right arrow over (C)}=0, 1,2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15. The swapping of column 0(col0)and column 3 (col3) in matrix {right arrow over (B)} is equivalentto swapping bits in the 4-bit counter as previously explained herein. Byswapping of column 0 and column 3 in matrix {right arrow over (B)}, anew sequence of numbers is produced. If {right arrow over (C)}′represents the new sequence of numbers, then {right arrow over (C)}′=0,8, 2, 10, 4, 12, 6, 14, 1, 9, 3, 11, 5, 13, 7, 15.

[0106] Thus, {right arrow over (C)}={right arrow over (B)}·{right arrowover (E)} appears as follows:

[0107] If {right arrow over (B)}′ represents the matrix {right arrowover (B)} after swapping column 0 and column 3 in matrix {right arrowover (B)}, then {right arrow over (C)}′={right arrow over (B)}′·{rightarrow over (E)} appears as follows: ${\begin{bmatrix}0000 \\1000 \\0010 \\1010 \\0100 \\1100 \\0110 \\1110 \\0001 \\1001 \\0011 \\1011 \\0101 \\1101 \\0111 \\1111\end{bmatrix}_{16 \times 4} \cdot \begin{bmatrix}2^{3} \\2^{2} \\2^{1} \\2^{0}\end{bmatrix}_{4 \times 1}} = \begin{bmatrix}0 \\8 \\2 \\10 \\4 \\12 \\6 \\14 \\1 \\9 \\3 \\11 \\5 \\13 \\7 \\15\end{bmatrix}_{16 \times 1}$

[0108] Memory Content and Address Pattern Sequences

[0109]FIG. 7 is a block diagram that illustrates the data format inmemory. Specifically, the format shown in FIG. 7 is a 4:2:0 chrominanceformat. In FIG. 7, blocks 704 a, 704 b, 704 c, and 704 d represent theluminance blocks, Y0, Y1, Y2, Y3. Blocks 704 e, and 704 f represent thechrominance blocks Cb and Cr. Blocks 704 a, 704 b, 704 c, 704 d, 704 e,and 704 f make up one macroblock. In each block, each word holds oneline or 8 pixels. Each block comprises 8 words. In such a case, amacroblock has 48 words. Thus, the format as shown in FIG. 7 needs a6-bit counter in order to generate 48 addresses (a 6-bit counter cangenerate up to 2⁶ addresses). Further, in FIG. 7, bit position display714 shows the 6 bits of the 6-bit counter. In bit position display 714,the most significant bit (MSB) 3 bits indicate the bits associated withthe block_index and the least significant bit (LSB) 3 bits indicate thebits associated with the word_index.

[0110] The block index takes the value of the counter's 3 MSB, i.e.,counter [5:3]. In the 4:4:4 format, the block index takes the value ofthe counter's 4 MSB, i.e., counter [6:3]. It is depicted in FIG. 7 inboth position and Maroblock/block position as well.

[0111] Word index takes the value of counter's 3 LSB, i e., counter[2:0]. It is depicted in FIG. 7 in both position and Maroblock/blockposition as well.

[0112] The description of the block index and word index are similarwith respect to all the figures from FIG. 8 to FIG. 20. Furthermore, thedescription of the block index and word index are similar with respectto all non-sequential sequences that are generated from the swappedcounter bits. For convenience, the description of the block index andword index are not repeated in all the figures.

[0113]FIG. 8 is a block diagram that illustrates three differentchrominance formats for a macroblock. In FIG. 8, the format 802 is a4:2:0 chrominance format, format 810 is a 4:2:2 chrominance format, andformat 820 is a 4:4:4 chrominance format. In the 4:2:0 chrominanceformat, blocks 804 are the luminance blocks and blocks 806 are thechrominance blocks. In the 4:2:2 chrominance format, blocks 812 are theluminance blocks and blocks 814 are the chrominance blocks. Similarly,in the 4:4:4 chrominance format, blocks 822 are the luminance blocks andblocks 824 are the chrominance blocks.

[0114]FIG. 9 is a block diagram that illustrates one address patternsequence that can be used for a 4:2:0 chrominance format. Blocks 906 arethe luminance blocks and blocks 908 are the chrominance blocks. FIG. 9also shows the counter bits 902, which six bits, from bit position [5]to bit position [0], are swapped to generate address pattern sequence904. Thus, the six counter bits 902 are rearranged as [5], [4], [0],[3], [2], [1] to generate address pattern sequence 904. Block 910illustrates the block index and word index of sequence 904 in decimalnumbers. Further, FIG. 9 shows the following:

[0115] address[5]<=counter[5];

[0116] address[4]<=counter[4];

[0117] address[3]<=counter[0];

[0118] address[2]<=counter[3];

[0119] address[1]<=counter[2];

[0120] address[0]<=counter[1].

[0121]FIG. 10 is a block diagram that illustrates one address patternsequence that can be used for a 4:2:2 chrominance format. Blocks 1006are the luminance blocks and blocks 1008 are the chrominance blocks.FIG. 10 also shows the counter bits 1002, which six bits, from bitposition [5] to bit position [0], are swapped to generate addresspattern sequence 1004. Thus, the six counter bits 1002 are rearranged as[5], [4], [0], [3], [2], [1] to generate address pattern sequence 1004.Block 1010 illustrates the block index and word index of sequence 1004in decimal numbers. Thus, FIG. 10 shows the following:

[0122] address[5]<=counter[5];

[0123] address[4]<=counter[4];

[0124] address[3]<=counter[0];

[0125] address[2]<=counter[3];

[0126] address[1]<=counter[2];

[0127] address[0]<=counter[1].

[0128]FIG. 11 is a block diagram that illustrates one address patternsequence that can be used for a 4:4:4 chrominance format. Blocks 1106are the luminance blocks and blocks 1108 are the chrominance blocks.FIG. 11 also shows the counter bits 1102, which seven bits, from bitposition [6] to bit position [0], are swapped to generate addresspattern sequence 1104. Thus, the seven counter bits 1102 are rearrangedas [6], [5], [4], [0], [3], [2], [1] to generate address patternsequence 1104. Block 1110 illustrates the block index and word index ofsequence 1104 in decimal numbers. Thus, FIG. 11 shows the following:

[0129] address[6]<=counter[6];

[0130] address[5]<=counter[5];

[0131] address[4]<=counter[4];

[0132] address[3]<=counter[0];

[0133] address[2]<=counter[3];

[0134] address[1]<=counter[2];

[0135] address[0]<=counter[1].

[0136] A combination of different bit swap pattern s can apply to asequence in a different data range to create a new non-sequentialsequence. In the FIG. 12, FIG. 15 and FIG. 17, the data range originallygenerated by a counter is called data index in the video decodingapplication.

[0137]FIG. 12 is a block diagram that illustrates one address patternsequence that can be used for a 4:2:0 chrominance format. Block 1206 arethe luminance blocks and blocks 1208 are the chrominance blocks. FIG. 12also shows the counter bits 1202, which bits are swapped to generateaddress pattern sequence 1204. In FIG. 12, four different bit swappatterns apply to four ranges of sequential sequences generated by acounter. The four ranges are block_index=3, block_index=4, block_index=5and the remaining, block_index=1, 2, 6.

[0138] When counter bits 1202 are in the block_index=3, the six counterbits 1202, from bit position [5] to bit position [0], are swapped togenerate address pattern sequence 1204. The following combinationallogic is applied to the six counter bits 1202: NOT [4], NOT [3], [0],[2], [1], NOT [5] to generate address pattern sequence 1204.

[0139] When counter bits 1202 are in the block_index=4, the six counterbits 1202, from bit position [5] to bit position [0], are swapped togenerate address pattern sequence 1204. The following combinationallogic is applied to the six counter bits 1202: [4], NOT [3], [0], [2],[1], [5] to generate address pattern sequence 1204.

[0140] When counter bits 1202 are in the block_index=5, the six counterbits 1202, from bit position [5] to bit position [0], are swapped togenerate address pattern sequence 1204. The following combinationallogic is applied to the six counter bits 1202: NOT [4], NOT [3], [0],[2], [1], [5] to generate address pattern sequence 1204.

[0141] When counter bits 1202 are in the block_index=1, 2, 6, the sixcounter bits 1202, from bit position [5] to bit position [0], areswapped to generate address pattern sequence 1204. The six counter bits1202 are rearranged as: [4], [3], [0], [2], [1], [5] to generate addresspattern sequence 1204.

[0142] Block 1210 illustrates the block index and word index of sequence1204 in decimal numbers.

[0143] Thus, with respect to FIG. 12, the following combinational logicapplies:

[0144] if (counter[5:3]=“011”)//block_index=3

[0145] address[5]<=not counter[4];

[0146] address[4]<=not counter[3];

[0147] address[3]<=counter[0];

[0148] address[2]<=counter[2];

[0149] address[1]<=counter[1];

[0150] address[0]<=not counter[5];

[0151] else if (counter[5:3]=“100”)//block_index=4

[0152] address[5]<=counter[4];

[0153] address[4]<=not counter[3];

[0154] address[3]<=counter[0];

[0155] address[2]<=counter[2];

[0156] address[1]<=counter[1];

[0157] address[0]<=counter[5];

[0158] else if (counter[5:3]=“101”)//block_index=5

[0159] address[5]<=not counter[4];

[0160] address[4]<=not counter[3];

[0161] address[3]<=counter[0];

[0162] address[2]<=counter[2];

[0163] address[1]<=counter[1];

[0164] address[0]<=counter[5];

[0165] else

[0166] address[5]<=counter[4];

[0167] address[4]<=counter[3],

[0168] address[3]<=counter[0];

[0169] address[2]<=counter[2];

[0170] address[1]<=counter[1];

[0171] address[0]<=counter[5];

[0172]FIG. 13 is a block diagram that illustrates one address patternsequence that can be used for a 4:2:2 chrominance format. Block 1306 arethe luminance blocks and blocks 1308 are the chrominance blocks. FIG. 13also shows the counter bits 1302, which six bits, from bit position [5]to bit position [0], are swapped to generate address pattern sequence1304. Thus, the six counter bits 1302 are rearranged as [4], [3], [0],[2], [1], [5], to generate address pattern sequence 1304. Block 1310illustrates the block index and word index of sequence 1304 in decimalnumbers. Thus, FIG. 13 shows the following:

[0173] address[5]<=counter[4];

[0174] address[4]<=counter[3];

[0175] address[3]<=counter[0],

[0176] address[2]<=counter[2];

[0177] address[1]<=counter[1];

[0178] address[0]<=counter[5].

[0179]FIG. 14 is a block diagram that illustrates one address patternsequence that can be used for a 4:4:4 chrominance format. Block 1406 arethe luminance blocks and blocks 1408 are the chrominance blocks. FIG. 14also shows the counter bits 1402, which seven bits, from bit position[6] to bit position [0], are swapped to generate address patternsequence 1304. Thus, the seven counter bits 1402 are rearranged as [5],[4], [3], [0], [2], [1], [6] to generate address pattern sequence 1404.Block 1410 illustrates the block index and word index of sequence 1404in decimal numbers. Thus, FIG. 14 shows the following:

[0180] address[6]<=counter[5];

[0181] address[5]<=counter[4];

[0182] address[4]<=counter[3];

[0183] address[3]<=counter[0];

[0184] address[2]<=counter[2];

[0185] address[1]<=counter[1];

[0186] address[0]<=counter[6].

[0187]FIG. 15 is a block diagram that illustrates one address patternsequence that can be used for a 4:2:0 chrominance format. Block 1506 arethe luminance blocks and blocks 1508 are the chrominance blocks. FIG. 15also shows the counter bits 1502, which bits are swapped to generateaddress pattern sequence 1504. In FIG. 15, three different bit swappatterns apply to three ranges of sequential sequences generated by acounter. The three ranges are block_index=2, block_index=3, 4, and theremaining, block_index=1, 5, 6.

[0188] When counter bits 1502 are in the block_index=2, the six counterbits 1502, from bit position [5] to bit position [0], are swapped togenerate address pattern sequence 1504. The six counter bits 1502 arerearranged as: [4], [5], [0], [3], [2], [1] to generate address patternsequence 1504.

[0189] When counter bits 1502 are in the block_index=3, 4, the sixcounter bits 1502, from bit position [5] to bit position [0], areswapped to generate address pattern sequence 1504. The followingcombinational logic is applied to the six counter bits 1502: [5], [4],[0], NOT[3], [2], [1] to generate address pattern sequence 1504.

[0190] When counter bits 1502 are in the block_index=1, 5, 6, the sixcounter bits 1502, from bit position [5] to bit position [0], areswapped to generate address pattern sequence 1504. The six counter bits1502 are rearranged as: [5], [4], [0], [3], [2], [1] to generate addresspattern sequence 1504.

[0191] Block 1510 illustrates the block index and word index of sequence1504 in decimal numbers.

[0192] Thus, with respect to FIG. 15, the following logic applies:

[0193] if (counter[5.3]=“010”)//block_index=2

[0194] address[5]<=counter[4];

[0195] address[4]<=counter[5];

[0196] address[3]<=counter[0];

[0197] address[2]<=counter[3];

[0198] address[1]<=counter[2];

[0199] address[0]<=counter[1];

[0200] else if (counter[5:3]=“011”orcounter[5:3]=“100”)//block_index=3,4

[0201] address[5]<=counter[5];

[0202] address[4]<=counter[4];

[0203] address[3]<=counter[0];

[0204] address[2]<=not counter[3];

[0205] address[1]<=counter[2];

[0206] address[0]<=counter[1];

[0207] else//block_index=1,5,6

[0208] address[5]<=counter[5];

[0209] address[4]<=counter[4];

[0210] address[3]<=counter[0];

[0211] address[2]<=counter[3];

[0212] address[1]<=counter[2];

[0213] address[0]<=counter[1].

[0214]FIG. 16 is a block diagram that illustrates one address patternsequence that can be used for a 4:2:2 chrominance format. Block 1606 arethe luminance blocks and blocks 1608 are the chrominance blocks. FIG. 16also shows the counter bits 1602, which six bits, from bit position [5]to bit position [0], are swapped to generate address pattern sequence1604. Thus, the six counter bits 1602 are rearranged as [4], [5], [0],[3], [2], [1] to generate address pattern sequence 1604. Block 1610illustrates the block index and word index of sequence 1604 in decimalnumbers. Thus, FIG. 16 shows the following:

[0215] address[5]<=counter[4];

[0216] address[4]<=counter[5];

[0217] address[3]<=counter[0];

[0218] address[2]<=counter[3];

[0219] address[1]<=counter[2];

[0220] address[0]<=counter[1].

[0221]FIG. 17 is a block diagram that illustrates one address patternsequence that can be used for a 4:4:4 chrominance format. Block 1706 arethe luminance blocks and blocks 1708 are the chrominance blocks. FIG. 17also shows the counter bits 1702, which bits are swapped to generateaddress pattern sequence 1704. In FIG. 17, three different bit swappatterns apply to three ranges of sequential sequence generated by acounter. The three ranges are block_index=6, 7, 8, 9, block_index=10,11, and the remaining, block_index=1, 2, 3, 4, 5.

[0222] When counter bits 1702 are in the block_index=6, 7, 8, 9, theseven counter bits 1702, from bit position [6] to bit position [0], areswapped to generate address pattern sequence 1704. The followingcombinational logic is applied to the seven counter bits 1702. NOT[6],NOT[5], NOT[4], [0], [3], [2], [1] to generate address pattern sequence1704.

[0223] When counter bits 1702 are in the block_index=10, 11, the sevencounter bits 1702, from bit position [6] to bit position [0], areswapped to generate address pattern sequence 1704. The seven counterbits 1702 are rearranged as: [6], [5], [4], [0], [3], [2], [1] togenerate address pattern sequence 1704.

[0224] When counter bits 1702 are in the block_index=1, 2, 3, 4, 5, theseven counter bits 1702, from bit position [6] to bit position [0], areswapped to generate address pattern sequence 1704. The seven counterbits 1702 are rearranged as: [5], [4], [6], [0], [3], [2], [1] togenerate address pattern sequence 1704.

[0225] Block 1710 illustrates the block index and word index of sequence1704 in decimal numbers.

[0226] Thus, with respect to FIG. 17, the following logic applies:

[0227] if (counter[6:4]=“011” orcounter[6:4]=“100”)//block_index=6,7,8,9

[0228] address[6]<=not counter[6];

[0229] address[5]<=not counter[5];

[0230] address[4]<=not counter[4];

[0231] address[3]<=counter[0];

[0232] address[2]<=counter[3];

[0233] address[1]<=counter[2];

[0234] address[0]<=counter[1];

[0235] else if (counter[5:3]=“101”)//block_index=10,11

[0236] address[6]<=counter[6];

[0237] address[5]<=counter[5];

[0238] address[4]<=counter[4];

[0239] address[3]<=counter[0];

[0240] address[2]<=counter[3];

[0241] address[1]<=counter[2];

[0242] address[0]<=counter[1];

[0243] else//block_index=1,2,3,4,5

[0244] address[6]<=counter[5];

[0245] address[5]<=counter[4];

[0246] address[4]<=counter[6];

[0247] address[3]<=counter[0];

[0248] address[2]<=counter[3];

[0249] address[1]<=counter[2];

[0250] address[0]<=counter[1];

[0251]FIG. 18 is a block diagram that illustrates one address patternsequence that can be used for a 4:2:0 chrominance format. Block 1806 arethe luminance blocks and blocks 1808 are the chrominance blocks. FIG. 18also shows the counter bits 1802, which bits are swapped to generateaddress pattern sequence 1804. In FIG. 18, two different bit swappatterns apply to two ranges of sequential sequences generated by acounter. The two ranges are block_index=0, 1, 2, 3, and the remaining,block_index=5, 6.

[0252] When counter bits 1802 are in the block_index=0, 1, 2, 3, the sixcounter bits 1802, from bit position [5] to bit position [0], areswapped to generate address pattern sequence 1804. The six counter bits1802 are rearranged as: [5], [3], [0], [2], [1], [4] to generate addresspattern sequence 1804.

[0253] When counter bits 1802 are in the block_index=5, 6, the sixcounter bits 1802, from bit position [5] to bit position [0], areswapped to generate address pattern sequence 1804. The six counter bits1802 are rearranged as: [5], [4], [0], [3], [2], [1] to generate addresspattern sequence 1804.

[0254] Block 1810 illustrates the block index and word index of sequence1804 in decimal numbers.

[0255] Thus, with respect to FIG. 18, the following logic applies: if(counter[5]=“0”)//block_index=0,1,2,3

[0256] address[5]<=counter[5];

[0257] address[4]<=counter[3];

[0258] address[3]<=counter[0];

[0259] address[2]<=counter[2];

[0260] address[1]<=counter[1];

[0261] address[0]<=counter[4];

[0262] else//block_index=5,6

[0263] address[5]<=counter[5];

[0264] address[4]<=counter[4];

[0265] address[3]<=counter[0];

[0266] address[2]<=counter[3];

[0267] address[1]<=counter[2];

[0268] address[0]<=counter[1].

[0269]FIG. 19 is a block diagram that illustrates one address patternsequence that can be used for a 4:2:2 chrominance format Block 1906 arethe luminance blocks and blocks 1908 are the chrominance blocks. FIG. 19also shows the counter bits 1902, which six bits, from bit position [5]to bit position [0], are swapped to generate address pattern sequence1904. Thus, the six counter bits 1902 are rearranged as [5], [3], [0],[2], [1], [4] to generate address pattern sequence 1904. Block 1910illustrates the block index and word index of sequence 1604 in decimalnumbers. Thus, FIG. 19 shows the following:

[0270] address[5]<=counter[5];

[0271] address[4]<=counter[3];

[0272] address[3]<=counter[0];

[0273] address[2]<=counter[2];

[0274] address[1]<=counter[1];

[0275] address[0]<=counter[4].

[0276]FIG. 20 is a block diagram that illustrates one address patternsequence that can be used for a 4:4:4 chrominance format. Block 2006 arethe luminance blocks and blocks 2008 are the chrominance blocks. FIG. 20also shows the counter bits 2002, which seven bits, from bit position[6] to bit position [0], are swapped to generate address patternsequence 2004 Thus, the seven counter bits 2002 are rearranged as [6],[5], [3], [0], [2], [1], [4] to generate address pattern sequence 2004.Block 2010 illustrates the block index and word index of sequence 2004in decimal numbers. Thus, FIG. 20 shows the following:

[0277] address[6]<=counter[6],

[0278] address[5]<=counter[5];

[0279] address[4]<=counter[3];

[0280] address[3]<=counter[0];

[0281] address[2]<=counter[2];

[0282] address[1]<=counter[1];

[0283] address[0]<=counter[4].

[0284] In the foregoing specification, the invention has been describedwith reference to specific embodiments thereof. It will, however, beevident that various modifications and changes may be made theretowithout departing from the broader spirit and scope of the invention.The specification and drawings are, accordingly, to be regarded in anillustrative rather than a restrictive sense.

What is claimed is:
 1. A method for decoding video signals, the methodcomprising the steps of: using an n-bit counter to generate up to nfactorial number of distinct bit pattern sequences, wherein n is apositive integer; selecting one or more of the n factorial number ofdistinct bit pattern sequences to create corresponding one or moreaddressing schemes; and fetching and storing data that is associatedwith the video signals using the one or more addressing schemes.
 2. Themethod of claim 1, wherein the step of using an n-bit counter togenerate up to n factorial number of distinct bit pattern sequencesfurther comprises the steps of: using the n-bit counter to produce afirst sequence of 2^(n) number of sequential numbers, wherein each ofthe 2^(n) sequential numbers is associated with a distinct binary valuecomprising n bits; and swapping an mth pair of bits in each binary valueto produce a (m+1)th sequence of 2^(n) number of non-sequential numbers,wherein m is an integer that ranges in value from 1 to (n!−1).
 3. Themethod of claim 1, wherein the step of selecting one or more of the nfactorial number of distinct bit pattern sequences further comprises thestep of using one or more corresponding multiplexers for selecting theone or more of the n factorial number of distinct bit pattern sequences.4. The method of claim 1, wherein the step of selecting one or more ofthe n factorial number of distinct bit pattern sequences furthercomprises the step of applying a combinational logic to one or more bitsof the n-bit counter.
 5. The method of claim 1, wherein the one or moreaddressing schemes is based on corresponding one or more flags andconditions that are associated with the video signals.
 6. A method fordecoding video signals, the method comprising the steps of: generating afirst bit pattern sequence to be associated with spatial data that isassociated with the video signals; generating a second bit patternsequence to be associated with temporal data that is associated with thevideo signals; generating a third bit pattern sequence to be associatedwith a combined data set comprising the spatial data and the temporaldata; and wherein: the first bit pattern sequence , the second bitpattern sequence and the third bit pattern sequence are distinct; andthe first bit pattern sequence , the second bit pattern sequence and thethird bit pattern sequence are generated using an n-bit counter.
 7. Acomputer-readable medium carrying one or more sequences of instructionsfor decoding video signals in a computer system, wherein execution ofthe one or more sequences of instructions by one or more processorscauses the one or more processors to perform the steps of: using ann-bit counter to generate up to n factorial number of distinct bitpattern sequences, wherein n is a positive integer; selecting one ormore of the n factorial number of distinct bit pattern sequences tocreate one or more corresponding addressing schemes; and fetching andstoring data that is associated with the video signals using the one ormore addressing schemes.
 8. An apparatus for decoding video signals,comprising: one or more n-bit counters, wherein each of the one or moren-bit counters can generate up to n factorial number of distinct bitpattern sequences, wherein n is a positive integer; and one or moremultiplexers corresponding to the one or more n-bit counters forselecting one or more of the n factorial number of distinct bit patternsequences to create one or more corresponding addressing schemes.
 9. Theapparatus of claim 8, further comprising one or more motion compensationunits that are associated with the one or more n-bit counters and theone or more corresponding multiplexers.
 10. The apparatus of claim 8,further comprising one or more merge-and-store inits that are associatedwith the one or more n-bit counters and the one or more correspondingmultiplexers.
 11. The apparatus of claim 8, further comprising one ormore intracoded direct cosine units that are associated with the one ormore n-bit counters and the one or more corresponding multiplexers. 12.The apparatus of claim 8, wherein: the one or more multiplexers are forselecting one or more of the n factorial number of distinct bit patternsequences.
 13. The apparatus of claim 8, wherein: the one or morecorresponding addressing schemes are used for fetching and storing datathat is associated with the video signals.
 14. The method of claim 8,wherein the one or more addressing schemes is based on corresponding oneor more flags and conditions that are associated with the video signals.